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NumonyxTM Wireless Flash Memory (W18/W30 SCSP)
32WQ and 64WQ Family with Asynchronous RAM
Datasheet
Product Features
Device Architecture -- Flash Density: 32-Mbit, 64-Mbit -- Async PSRAM Density: 16-Mbit, 32-Mbit -- Top, Bottom or Dual flash parameter configuration Device Voltage -- Flash VCC = 1.8 V; Flash VCCQ = 1.8 V or 3.0 V -- RAM VCC = 1.8 V or 3.0 V Device Packaging -- 88 balls (8 x 10 active ball matrix) -- Area: 8x10 mm -- Height: 1.2 mm to 1.4 mm PSRAM Performance -- 70 ns initial access, 25 ns async page reads at 1.8 V I/O -- 70 ns initial access async PSRAM at 1.8 V I/O -- 70 ns initial access, 25 ns async page reads at 3.0 V I/O SRAM Performance -- 70 ns initial access at 1.8 V or 3.0 V I/O Quality and Reliability -- Extended Temperature: -25 C to +85 C -- Minimum 100K flash block erase cycle -- 90 nm ETOXTM IX flash technology -- 130 nm ETOXTM VIII flash technology Flash Performance -- 65 ns initial access at 1.8 V I/O -- 70 ns initial access at 3.0 V I/O -- 25 ns async page at 1.8 V or 3.0 V I/O -- 14 ns sync reads (tCHQV) at 1.8 V I/O -- 20 ns sync reads (tCHQV) at 3.0 V I/O -- Enhanced Factory Programming: 3.10 s/Word (Typ) Flash Architecture -- Read-While-Write/Erase -- Asymmetrical blocking structure -- 4-KWord parameter blocks (Top or Bottom) -- 32-KWord main blocks -- 4-Mbit partition size -- 128-bit One-Time Programmable (OTP) Protection Register -- Zero-latency block locking -- Absolute write protection with block lock using F-VPP and F-WP# Flash Software -- NumonyxTM Flash Data Integrator (FDI) and Common Flash Interface (CFI)
Order Number: 251407-13 November 2007
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYXTM PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.
LL egal Lines and Disclaim ers
Numonyx B.V. may make changes to specifications and product descriptions at any time, without notice. Numonyx B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at http://www.numonyx.com. Numonyx, the Numonyx logo, and StrataFlash are trademarks or registered trademarks of Numonyx B.V. or its subsidiaries in other countries. *Other names and brands may be claimed as the property of others. Copyright (c) 2007, Numonyx B.V., All Rights Reserved.
Datasheet 2
November 2007 Order Number: 251407-13
32WQ and 64WQ Family with Asynchronous RAM
Contents
1.0 Introduction .............................................................................................................. 6 1.1 Nomenclature ..................................................................................................... 6 1.2 Conventions ....................................................................................................... 7 Functional Overview .................................................................................................. 8 2.1 Block Diagram .................................................................................................... 8 2.2 Flash Memory Map and Partitioning........................................................................ 9 Package Information ............................................................................................... 10 Ballout and Signal Description ................................................................................. 13 4.1 Signal Ballout ................................................................................................... 13 4.2 Signal Descriptions ............................................................................................ 14 Maximum Ratings and Operating Conditions............................................................ 16 5.1 Absolute Maximum Ratings................................................................................. 16 5.2 Operating Conditions ......................................................................................... 16 5.3 Capacitance...................................................................................................... 17 Electrical Specifications ........................................................................................... 18 6.1 DC Characteristics ............................................................................................. 18 AC Characteristics ................................................................................................... 20 7.1 Flash AC Characteristics ..................................................................................... 20 7.2 SRAM AC Characteristics .................................................................................... 20 7.3 PSRAM AC Characteristics................................................................................... 22 7.4 Device AC Test Conditions .................................................................................. 27 Flash Power Consumption ....................................................................................... 28 Device Operation ..................................................................................................... 29 9.1 Bus Operations ................................................................................................. 29
2.0
3.0 4.0
5.0
6.0 7.0
8.0 9.0
10.0 Flash Command Definitions ..................................................................................... 33 11.0 Flash Read Operations............................................................................................. 33 12.0 Flash Program Operations ....................................................................................... 33 13.0 Flash Erase Operations ............................................................................................ 33 14.0 Flash Security Modes ............................................................................................... 33 15.0 Flash Read Configuration Register ........................................................................... 33 16.0 SRAM Operations..................................................................................................... 34 16.1 Power-up Sequence and Initialization ................................................................... 34 16.2 Data Retention Mode ......................................................................................... 34 17.0 PSRAM Operations................................................................................................... 36 17.1 Power-Up Sequence and Initialization................................................................... 36 17.1.1 16Mbit PSRAM Power-Up Sequence (Non-Page Mode).................................. 36 17.2 Standby Mode/ Deep Power-Down Mode............................................................... 37 17.3 PSRAM Special Read and Write Constraints ........................................................... 37 A B C D Write State Machine ................................................................................................ 38 Common Flash Interface.......................................................................................... 38 Flash Flowcharts ..................................................................................................... 38 Additional Information ............................................................................................ 38
November 2007 Order Number: 251407-13
Datasheet 3
32WQ and 64WQ Family with Asynchronous RAM
E F
Ordering Information (Active Line Items) ................................................................39 Ordering Information (Retired Line Items) ..............................................................40
Datasheet 4
November 2007 Order Number: 251407-13
32WQ and 64WQ Family with Asynchronous RAM
Revision History
Date June 2003 September 2003 May 2004 August 2004
Revision -001 -002 -006 -007 Initial release
Description
Changed PSRAM Read values. Added new Transient Equivalent Testing Load Circuit figure. General text edits. Reformatted the datasheet and moved sections around according to the new layout. Added 90 nm product information. Added line items. Added DC and AC specs for the new line items and edits to related sections. Added line items. Added 32WQ product information. Added line items. Removed Power-up sequence from Section 16; Added 70ns PSRAM (non-page mode) specification Updated Ordering Information Updated Ordering information with active and retired line items. Updated AC spec & power-up specs for 38F2030W0YxQE & 38F2040W0YxQE Rempved 38F2030W0YxQE & 38F2040W0YxQE Line Items Updated ordering information Applied Numonyx branding.
January 2005 June 2005 October 2005 June 2007 August 2007 November 2007
-008 -009 -010 -011 -012 13
November 2007 Order Number: 251407-13
Datasheet 5
32WQ and 64WQ Family with Asynchronous RAM
1.0
Introduction
This document contains information pertaining to the products in the NumonyxTM Wireless Flash Memory (W18/W30 SCSP) family with asynchronous RAM. The W18/ W30 SCSP 32WQ and 64WQ families offer a wide variety of stacked combinations that include single flash die, two flash die, flash + PSRAM, and flash + SRAM options. This document provides information where this SCSP family differs from the Numonyx Wireless Flash Memory (W18/W30) discrete device. Refer to the discrete datasheets NumonyxTM Wireless Flash Memory (W18) Datasheet (order number 290701) and NumonyxTM Wireless Flash Memory (W30) Datasheet (order number 290702) for flash product details not included in this SCSP datasheet. The Numonyx Wireless Flash Memory (W18/W30 SCSP) family offers various flash plus static RAM combinations in a common package footprint. The flash memory features 1.8 V low-power operations with flexible, multi-partition, dual-operation Read-WhileWrite / Read-While-Erase, asynchronous, and synchronous reads. This SCSP device integrates up to two flash die, and one PSRAM or SRAM die in a low-profile package compatible with other SCSP families with QUAD+ ballout.
1.1
Nomenclature
0x 0b Byte CFI CUI DU ETOX FDI K(noun) Kb KB Kword M (noun) Mb MB OTP PLR PR PRD RCR Hexadecimal prefix Binary prefix 8 bits Common Flash Interface Command User Interface Don't Use EPROM Tunnel Oxide NumonyxTM Flash Data Integrator (software solution) 1 thousand 1024 bits 1024 bytes 1024 words 1 million 1,048,576 bits 1,048,576 bytes One-Time Programmable Protection Lock Register Protection Register Protection Register Data Read Configuration Register
Datasheet 6
November 2007 Order Number: 251407-13
32WQ and 64WQ Family with Asynchronous RAM
RFU SCSP SR SRD Word WSM
Reserved for Future Use Stacked Chip Scale Package Status Register Status Register Data 16 bits Write State Machine
1.2
Conventions
Group Membership Brackets: Square brackets are used to designate group membership or to define a group of signals with a similar function, such as A[21:1] and SR[4,1]. VCC vs. VCC: When referring to a signal or package-connection name, the notation used is VCC, etc. When referring to a timing or electrical level, the notation used is subscripted such as VCC, etc. Device: This term is used interchangeably throughout this document to denote either a particular die, or the combination of multiple die within a single package. F[3:1]-CE#, F[2:1]-OE#: This is the method used to refer to more than one chipenable or output enable at the same time. When each is referred to individually, the reference will be F1-CE# and F1-OE# (for die #1), and F2-CE# and F2-OE# (for die #2). F-VCC, P-VCC or S-VCC: When referencing flash memory signals or timings, the notation used is F-VCC or F-VCC, respectively. When the reference is to PSRAM signals or timings, the notation is prefixed with "P-" (e.g., P-VCC, P-VCC). When referencing SRAM signals or timings, the notation is prefixed with "S-" (e.g., S-VCC or S-VCC). PVCC and S-VCC are RFU for stacked combinations that do not include PSRAM or SRAM. R-OE#, R-LB#, R-UB#, R-WE#: These are used to identify RAM OE#, LB#, UB#, WE# signals, and are usually shared between 2 or more RAM die. R-OE#, R-LB#, RUB# and R-WE are RFU for stacked combinations that do not include PSRAM or SRAM.
November 2007 Order Number: 251407-13
Datasheet 7
32WQ and 64WQ Family with Asynchronous RAM
2.0
Functional Overview
This section provides an overview of the features and capabilities of the Numonyx Wireless Flash Memory (W18/W30 SCSP) family with asynchronous RAM device. The W18/W30 SCSP device provides flash + RAM die combinations. Products range from single flash die, two flash die, flash + PSRAM, or flash + SRAM. You can choose a W18 SCSP device or a W30 SCSP device with SRAM or PSRAM offered with the same package footprint and signal ballout.
2.1
Block Diagram
Show here are all internal package connections for the SCSP family with multiple die. See Table 21, "Ordering Information on Active Line Items" on page 40 for valid combinations of flash and RAM die. Unused connections on combinations with less than three die are reserved and should not be used. Please contact your local Numonyx representative for details regarding any reserved or RFU pins.
Figure 1:
Block Diagram
F2-VCC F2-CE# F2-OE#
Flash Die #2 32- or 64-Mbit W18/W30
CLK ADV# F-WP# F-RST#
F-WE# F-VPP VCCQ WAIT
F1-OE# F1-CE# F1-VCC A[MAX:0]
Flash Die #1 32- or 64-Mbit W18/W30
VSS D[15:0]
S-VCC/P-VCC P-CS#/S-CS1# S-CS2 R-OE#
RAM Die 4-, 8-, 16-Mbit SRAM or 16- or 32-Mbit PSRAM
R-WE# P-MODE R-UB# R-LB#
Datasheet 8
November 2007 Order Number: 251407-13
32WQ and 64WQ Family with Asynchronous RAM
2.2
Flash Memory Map and Partitioning
Consult the latest NumonyxTM Wireless Flash Memory (W18) Datasheet (order number 290701) and the NumonyxTM Wireless Flash Memory (W30) Datasheet (order number 290702), for individual flash die memory map and partitioning information. Table 1 and Table 2 show memory map and partitioning information for dual-flash memory die configurations. Flash Die #1 (with F1-CE# as its Chip Select) is configured as a bottom parameter while Flash Die #2 (with F2-CE# as its Chip Select) is configured as top parameter.
November 2007 Order Number: 251407-13
Datasheet 9
32WQ and 64WQ Family with Asynchronous RAM
3.0
Package Information
The following two packages are offered with the 32WQ and 64WQ Family.
Figure 2:
Mechanical Specifications for 1- or 2-Die SCSP Device (8x10x1.2 mm)
A1 Index Mark
1 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1 S2 A B C D E F G H J K L M D A B C D E F G H J K L M b E e S1
Top View - Ball Down
A2 A1
Bottom View - Ball Up
A
Y
Drawing not to scale.
Dimensions Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Length Package Body Width Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along E Corner to Ball A1 Distance Along D
Symbol A A1 A2 b D E e N Y S1 S2
Min 0.200 0.325 9.900 7.900
Millimeters Nom Max 1.200 0.860 0.375 10.000 8.000 0.800 88 1.200 0.600
Notes
Min 0.0079
Inches Nom
Max 0.0472
0.425 10.100 8.100
0.0128 0.3898 0.3110
0.0339 0.0148 0.3937 0.3150 0.0315 88 0.0472 0.0236
0.0167 0.3976 0.3189
1.100 0.500
0.100 1.300 0.700
0.0433 0.0197
0.0039 0.0512 0.0276
Datasheet 10
November 2007 Order Number: 251407-13
32WQ and 64WQ Family with Asynchronous RAM
Figure 3:
A1 Index Mark
Mechanical Specifications for Triple-Die SCSP Device (8x10x1.4 mm)
S1 1 2 3 4 5 6 7 8 A B C D E D F G H J K L M b E e 8 7 6 5 4 3 2 1 S2 A B C D E F G H J K L M
Top View - Ball Down
A2 A1
Bottom View - Ball Up
A
Y
Drawing not to scale.
Millimeters Nom Max 1.400 1.070 0.375 10.000 8.000 0.800 88 1.200 0.600 Inches Nom
Dimensions Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Length Package Body Width Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along E Corner to Ball A1 Distance Along D
Symbol A A1 A2 b D E e N Y S1 S2
Min 0.200 0.325 9.900 7.900
Notes
Min 0.0079
Max 0.0551
0.425 10.100 8.100
0.0128 0.3898 0.3110
0.0421 0.0148 0.3937 0.3150 0.0315 88 0.0472 0.0236
0.0167 0.3976 0.3189
1.100 0.500
0.100 1.300 0.700
0.0433 0.0197
0.0039 0.0512 0.0276
November 2007 Order Number: 251407-13
Datasheet 11
32WQ and 64WQ Family with Asynchronous RAM
Table 1:
64-Mbit Flash + 32-Mbit Flash Die W18/W30 SCSP Memory Map and Partitioning
Partitioning Block Size (KW) Block # Address Range
Parameter Partition Flash Die #2 (32-Mbit) Top Parameter
Partition 0 Partition 1
4 32 32 32 32 32
63-70 56-62 48-55 40-47 32-39 0-31
1F8000-1FFFFF 1C0000-1F7FFF 180000-1BFFFF 140000-17FFFF 100000-13FFFF 000000-0FFFFF
Main Partitions
Partition 2 Partition 3 Partitions 4-7
Partitions 8-15 Partitions 4-7 Flash Die #1 (64-Mbit) Bottom Parameter Main Partitions Partition 3 Partition 2 Partition 1 Parameter Partition Partition 0
32 32 32 32 32 32 4
71-134 39-70 31-38 23-30 15-22 8-14 0-7
200000-3FFFFF 100000-1FFFFF 0C0000-0FFFFF 080000-0BFFFF 040000-07FFFF 008000-03FFFF 000000-007FFF
Table 2:
64-Mbit Dual-Flash Die W18/W30 SCSP Memory Map and Partitioning
Partitioning Block Size (KW) Block # Address Range
Parameter Partition Flash Die #2 (64-Mbit) Top Parameter
Partition 0 Partition 1 Partition 2
4 32 32 32 32 32 32
127-134 120-126 112-119 104-111 96-103 64-95 0-63
3F8000-3FFFFF 3C0000-3F7FFF 380000-3BFFFF 340000-37FFFF 300000-33FFFF 200000-2FFFFF 000000-1FFFFF
Main Partitions
Partition 3 Partitions 4-7 Partitions 8-15
Partitions 8-15 Partitions 4-7 Flash Die #1 (64-Mbit) Bottom Parameter Main Partitions Partition 3 Partition 2 Partition 1 Parameter Partition Partition 0
32 32 32 32 32 32 4
71-134 39-70 31-38 23-30 15-22 8-14 0-7
200000-3FFFFF 100000-1FFFFF 0C0000-0FFFFF 080000-0BFFFF 040000-07FFFF 008000-03FFFF 000000-007FFF
Datasheet 12
November 2007 Order Number: 251407-13
32WQ and 64WQ Family with Asynchronous RAM
4.0
4.1
Ballout and Signal Description
Signal Ballout
Figure 4 shows the 32WQ and 64WQ W18/W30 SCSP family 88-ball (8x10 active ball matrix) device.
Figure 4:
88-Ball (8x10 Active Ball Matrix) QUAD+ Ballout
Pin 1
1 2 3 4 5 6 7 8
A
DU
DU
DU
DU
A
B
A4
A18
A19
VSS
F1-VCC
F2-VCC
A21
A11
B
C
A5
R-LB#
A23
VSS
S-CS2
CLK
A22
A12
C
D
A3
A17
A24
F-VPP
R-WE#
P1-CS#
A9
A13
D
E
A2
A7
A25
F-WP#
ADV#
A20
A10
A15
E
F
A1
A6
R-UB#
F-RST#
F-WE#
A8
A14
A16
F
G
A0
DQ8
DQ2
DQ10
DQ5
DQ13
WAIT
F2-CE#
G
H
R-OE#
DQ0
DQ1
DQ3
DQ12
DQ14
DQ7
F2-OE#
H
J
S-CS1#
F1-OE#
DQ9
DQ11
DQ4
DQ6
DQ15
VCCQ
J
K
F1-CE#
P2-CS#
F3-CE#
S-VCC
P-VCC
F2-VCC
VCCQ
P-Mode/ P-CRE
K
L
VSS
VSS
VCCQ
F1-VCC
VSS
VSS
VSS
VSS
L
M
DU
DU
DU
DU
M
1
2
3
4
5
6
7
8
Top View - Ball Side Down
Global Signals De-Populated Balls Flash Specific SRAM/PSRAM Specific Do Not Use
Legend:
November 2007 Order Number: 251407-13
Datasheet 13
32WQ and 64WQ Family with Asynchronous RAM
4.2
Table 3:
Symbol
Signal Descriptions
Signal Descriptions (Sheet 1 of 2)
Type Name and Function ADDRESS INPUTS: Inputs for all die addresses during read and write operations. Addresses are internally latched during write operations. * 4-Mbit: A[17:0] * 8-Mbit: A[18:0] * 16-Mbit: A[19:0] * 32-Mbit: A[20:0] * 64-Mbit: A[21:0] A0 is the lowest-order word address. A[25:22] denote high-order addresses reserved for future device densities DATA INPUTS/OUTPUTS: Inputs data and commands during write cycles; outputs data during read cycles. Data signals float when the device or its outputs are deselected. Data are internally latched during writes. FLASH CLOCK: CLK synchronizes the selected flash die to the memory bus frequency in synchronous-read mode. During synchronous read operations, the initial address is latched on the rising edge of ADV#, or the rising/ falling edge of CLK when ADV# is low, whichever occurs first. CLK is only used in synchronous-read mode. Refer to the flash discrete product datasheet for information on how to use this signal in asynchronous-read mode. FLASH ADDRESS VALID: Low-true; During synchronous read operations, the initial address is latched on the rising edge of ADV#, or the rising/ falling edge of CLK when ADV# is low, whichever occurs first. Refer to the flash discrete product datasheet for information on how to use this signal in asynchronous-read mode. FLASH WAIT: When asserted, WAIT indicates invalid data from the selected flash die on D[15:0]. WAIT is High-Z whenever the flash die is deselected (CE# = VIL). WAIT is not gated by OE#. WAIT is only used in synchronous array-read mode. Refer to the flash discrete product datasheet for information on how to use this signal in asynchronous-read mode. FLASH CHIP ENABLE: Low-true; CE#-low selects the associated flash memory die. When asserted, flash internal control logic, input buffers, decoders, and sense amplifiers are active. When deasserted, the associated flash die is deselected; power is reduced to standby levels, data and WAIT outputs are placed in High-Z. F1-CE# selects flash die #1; F2-CE# selects flash die #2 and is RFU on combinations with only one flash die. F3-CE# selects flash die #3 and is RFU on SCSP combinations with only one or two flash die. SRAM CHIP SELECTS: When both SRAM chip selects are asserted, SRAM internal control logic, input buffers, decoders, and sense amplifiers are active. When either/both SRAM chip selects are deasserted (S-CS1# = VIH and/or S-CS2 = VIL), the SRAM is deselected and its power is reduced to standby levels. S-CS1# and S-CS2 are only available on SCSP combinations with SRAM die. PSRAM CHIP SELECTS: Low-true; When asserted, PSRAM internal control logic, input buffers, decoders, and sense amplifiers are active. When deasserted, the PSRAM is deselected and its power is reduced to standby levels. P1-CS# selects PSRAM die #1 and is available only on SCSP combinations with PSRAM die. This ball is RFU on SCSP combinations without PSRAM. P2-CS# selects PSRAM die #2 and is available only on SCSP combinations with two PSRAM die. This ball is RFU on SCSP combinations without PSRAM or with a single PSRAM. FLASH OUTPUT ENABLE: Low-true; OE#-low enables the flash output buffers. OE#-high disables the flash output buffers, and places the flash outputs in High-Z. F1-OE# controls the outputs of flash die #1; F2-OE# controls the outputs of flash die #2 and #3, and is available only on SCSP combinations with two or three flash die and is RFU on SCSP combinations with only one flash die. RAM OUTPUT ENABLE: Low-true; R-OE#-low enables the RAM output buffers. R-OE#-high disables the RAM output buffers, and places the RAM outputs in High-Z. R-OE# is only available on SCSP combinations with RAM die.
A[21:0]
Input
D[15:0]
Input/ Output
CLK
Input
ADV#
Input
WAIT
Output
F[3:1]-CE#
Input
S-CS1# S-CS2
Input
P[2:1]-CS#
Input
F[2:1]-OE#
Input
R-OE#
Input
Datasheet 14
November 2007 Order Number: 251407-13
32WQ and 64WQ Family with Asynchronous RAM
Table 3:
Symbol R-UB# R-LB# F-WE# R-WE#
Signal Descriptions (Sheet 2 of 2)
Type Input Name and Function RAM UPPER/ LOWER BYTE ENABLES: Low-true; During RAM reads, R-UB#-low enables the RAM high-order bytes on D[15:8], and R-LB#-low enables the RAM low-order bytes on D[7:0]. R-UB# and R-LB# are only available on SCSP combinations with either SRAM die or PSRAM die. FLASH WRITE ENABLE: Low-true; WE# controls writes to the selected flash die. Address and data are latched on the rising edge of WE#. RAM WRITE ENABLE: Low-true; R-WE# controls writes to the RAM die. R-WE# is only available on SCSP combinations with RAM die. FLASH WRITE PROTECT: Low-true; WP# enables/disables the lock-down protection mechanism of the flash die. WP#-low enables the lock-down mechanism- locked down blocks cannot be unlocked with software commands. WP#-high disables the lock-down mechanism, allowing locked down blocks to be unlocked with software commands. FLASH RESET: Low-true; RST#-low initializes flash internal circuitry and disables flash operations. RST#-high enables flash operation. Exit from reset places the flash in asynchronous read array mode. FLASH PROGRAM/ ERASE POWER: A valid F-VPP voltage on this ball enables flash program/erase operations. Flash memory array contents cannot be altered when F-VPP(VPEN) < VPPLK(VPENLK). Erase/ program operations at invalid F-VPP(VPEN) voltages should not be attempted. Refer to the flash discrete product datasheet for additional details. F-VPEN (Erase/Program/Block Lock Enables) is not available for W18/W30 products. PSRAM MODE: Low-true; P-MODE is used to enter/exit low power mode. Low power mode is not applicable to 38F2020W0ZTQ1, 38F2020W0ZBQ1, 38F2030W0YTQ1, 38F2030W0YBQ1, 38F2030W0ZTQ2, 38F2030W0ZBQ2, 38F1030W0ZTQ0, 38F1030W0ZBQ0. P-Mode is only available on SCSP combinations with PSRAM die. FLASH LOGIC POWER: F1-VCC supplies power to the core logic of flash die #1; F2-VCC supplies power to the core logic of flash die #2 and #3. Write operations are inhibited when F-VCC < VLKO. Device operations at invalid F-VCC voltages should not be attempted. F2-VCC is only available on SCSP combinations with two or three flash die, and is RFU on SCSP combinations with only one flash die. SRAM Power Supply: Supplies power to the SRAM die. S-VCC is only available on SCSP combinations with SRAM die. PSRAM Power Supply: Supplies power to the PSRAM die. P-VCC is only available on SCSP combinations with PSRAM die. FLASH OUTPUT-BUFFER POWER: Supplies power for the I/O output buffers. Ground: Connect to ground. Do not float any VSS connection. Reserved for Future Use: Reserve for future device functionality/ enhancements. Don't Use: Do not connect to any other signal, or power supply; must be left floating.
Input Input
F-WP#
Input
F-RST#
Input
F-VPP F-VPEN
Power
P-MODE
Input
F[2:1]-VCC
Power
S-VCC P-VCC VCCQ VSS RFU DU
Power Power Power Power -- --
November 2007 Order Number: 251407-13
Datasheet 15
32WQ and 64WQ Family with Asynchronous RAM
5.0
5.1
Warning:
Maximum Ratings and Operating Conditions
Absolute Maximum Ratings
Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only.
NOTICE: This document contains information available at the time of its release. The specifications are subject to change without notice. Verify with your local Numonyx sales office that you have the latest datasheet before finalizing a design.
Table 4:
Parameter
Absolute Maximum Ratings
Min -25 -55 1.8 V I/O 3.0 V I/O -0.2 -0.2 -0.5 1.8 V I/O 3.0 V I/O -0.2 -0.2 -0.2 - Max +85 +125 +2.45 +3.6 +2.45 +2.45 +3.6 +14.0 100 Unit C C V V V V V V mA 1,2,3 2,3 2,3 1,2,3 2,3 2,3,4,5 6 Notes 7
Temperature under Bias Extended Storage Temperature Voltage On Any Signal (except F[2:1]-VCC, VCCQ, F-VPP, S-VCC and P-VCC) F[2:1]-VCC Voltage VCCQ, S-VCC and P-VCC Voltage F-VPP Voltage ISH Output Short Circuit Current
Notes: 1. 90 nm is only avail with the 1.8 V I/O. 2. All Specified voltages are relative to VSS. Minimum DC voltage is -0.2 V on input/output signals, -0.2 V on F[2:1]-VCC and F-VPP signals. For 90 nm devices, during transitions, this level may overshoot to -1.5 V for periods < 20 ns, during transitions, may overshoot to F-VCC + 1.5 V for periods < 20 ns. 3. All Specified voltages are relative to VSS. Minimum DC voltage is -0.2 V on input/output signals, -0.2 V on F[2:1]-VCC and F-VPP signals. For 130 nm devices, during transitions, this level may overshoot to -2 V for periods < 20 ns, during transitions, may overshoot to F-VCC + 2 V for periods < 20 ns. 4. Maximum DC voltage on F-VPP may overshoot to +14.0 V for periods < 20 ns. 5. F-VPP program voltage is normally VPPL. The maximum DC voltage on F-VPP may overshoot to +14 V for periods < 20 ns. F-VPP can be VPPH for 1000 erase cycles on main blocks, 2500 cycles on parameter blocks. 6. Output shorted for no more than one second. No more than one output shorted at a time. 7. Devices available with -30o C temperature specifications are: 38F2020W0ZTQ1, 38F2020W0ZBQ1, 38F2030W0YTQ1, 38F2030W0YBQ1, 38F2030W0ZTQ2, 38F2030W0ZBQ2, 38F1030W0ZTQ0, 38F1030W0ZBQ0, 38F2030W0YTQF, 38F2030W0YBQF, 38F2040W0YTQF, 38F2040W0YBQF
5.2
Warning:
Operating Conditions
Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.
Table 5:
Symbol
Operating Conditions (Sheet 1 of 2)
Parameter Flash + Flash Min Max +85 1.95 Flash + SRAM Min -25 1.7 Max +85 1.95 Flash + PSRAM Min -25 1.7 Max +85 1.95 C V 2 Unit Notes
TC F-VCC
Operating Temperature Flash Supply Voltage
-25 1.7
Datasheet 16
November 2007 Order Number: 251407-13
32WQ and 64WQ Family with Asynchronous RAM
Table 5:
VCCQ S-VCC P-VCC VPPL VPPH Note: 1. 2.
Operating Conditions (Sheet 2 of 2)
Flash I/O Voltage PSRAM and SRAM Supply Voltage Flash Program Logic Level Flash Factory Program Voltage 3.0 V I/O 1.8 V I/O 2.2 1.7 0.9 11.4 3.3 1.95 1.95 12.6 2.2 1.7 0.9 11.4 3.3 1.95 1.95 12.6 2.7 1.8 0.9 11.4 3.1 1.95 1.95 12.6 V V V V 1
F-VPP is normally VPPL. F-VPP can be connected to 11.4 V-12.6 V for 1000 cycles on main blocks for extended temperatures and 2500 cycles on parameter blocks at extended temperature. Devices available with -30o C temperature specifications are: 38F2020W0ZTQ1, 38F2020W0ZBQ1, 38F2030W0YTQ1, 38F2030W0YBQ1, 38F2030W0ZTQ2, 38F2030W0ZBQ2, 38F1030W0ZTQ0, 38F1030W0ZBQ0, 38F2030W0YTQF, 38F2030W0YBQF, 38F2040W0YTQF, 38F2040W0YBQF
5.3
Capacitance
NOTICE: Refer to the NumonyxTM Wireless Flash Memory (W18) Datasheet (order number 290701) and NumonyxTM Wireless Flash Memory (W30) Datasheet (order number 290702) for flash capacitance details. For SCSP products with two flash die, flash capacitances for each of the flash die need to be considered accordingly.
Table 6:
Symbol CIN COUT
SRAM, PSRAM Capacitance
Parameter Input Capacitance Output Capacitance Typ 10 10 Unit pF pF Condition VIN = 0.0 V, Tc = 25 C, f = 1 MHz VOUT = 0.0 V, Tc = 25 C, f = 1 MHz
November 2007 Order Number: 251407-13
Datasheet 17
32WQ and 64WQ Family with Asynchronous RAM
6.0
6.1
Electrical Specifications
DC Characteristics
SRAM and PSRAM DC characteristics are shown in Table 7 and Table 8. Refer to the Numonyx Wireless Flash Memory (W18) Datasheet (order number 290701) and the Numonyx Wireless Flash Memory (W30) Datasheet (order number 290702) for flash DC characteristics.
Table 7:
Parameter S-VCC VDR
SRAM DC Characteristics
1.8 V SRAM Description Voltage Range VCC for Data Retention 4M Operating Current at min cycle time Test Conditions Min 1.7 1.0 - - - - - - - - - - - - S-VCC 0.15 -0.1 S-VCC 0.4 -0.2 - - -0.2 < VIN < S-VCC + 0.2 V -0.2 < VIN < S-VCC + 0.2 V S-VCC = VDR -1 -1 Max 1.95 - 25 35 40 4 6 10 12 20 30 6 10 18 - 0.2 S-VCC+ 0.2 0.4 - - +1 +1 Min 2.2 1.5 - - - - - - - - - - - - S-VCC 0.1 -0.1 S-VCC 0.4 -0.2 - - -1 -1 Max 3.3 - 45 50 55 10 10 15 15 25 45 5 12 15 - 0.1 S-VCC + 0.2 0.6 - - +1 +1 V V V V mA mA A A A A mA mA V V 3.0 V SRAM Unit
ICC
IIO = 0 mA
8M 16M 4M
ICC2
Operating Current at max cycle time (1 s)
IIO = 0 mA
8M 16M
ISB
Standby Current
S-CS1# S-VCC-0.2V or S-CS2 VSS +0.2V Address/Data toggling at minimum cycle time 1.8 V SRAM: S-VCC = 1.0 V 3.0 V SRAM: S-VCC = 1.5 V IOH = -100 A IOL = 100 A, VCCMIN
4M 8M 16M 4M 8M 16M
IDR
Current in Data Retention mode
VOH VOL VIH VIL IOH IOL *IIL *ILDR
Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Output HIGH Current Output LOW Current Input Leakage Current Input Leakage Current in Data Retention Mode
* Input leakage currents include Hi-Z output leakage for bi-directional buffers with tri-state outputs.
Datasheet 18
November 2007 Order Number: 251407-13
32WQ and 64WQ Family with Asynchronous RAM
Table 8:
Parameter
PSRAM DC Characteristics
1.8 V PSRAM Description Test Conditions Min Max 1.95 - 30 20 35 - 5 - - 100 - Min 2.7 - - - - - - - - - - Max 3.1 30 35 - 45 5 7 7 80 100 85 A 2, 4 mA 2 V mA mA mA 2 3 2 3.0 V PSRAM Unit Notes
VCC
Voltage Range 8M
1.8 - - - - - - - - - -
ICC
Operating Current at min cycle time
IIO = 0 mA
16M 16M 32M
ICC2
Operating Current at max cycle time (1 s)
8M IIO = 0 mA 16M 32M P-CS# P-VCC0.2V. All inputs stable (either high or low) 8M 16M 16M
ISB
Standby Current
P-CS# P-VCC0.2V or P-Mode P-VCC0.2V Address/Data toggling at minimum cycle time P-Mode 0.2 V IOH = -0.5 mA IOH = -0.1 mA IOL = 1 mA,
32M
-
100
-
100
A
2, 5
Isbd
Deep PowerDown
16M 32M
- - 0.8P VCC 1.4 - -0.1 0.8P -VCC P-VCC 0.3 -0.3 -0.2
- 30 - - 0.2P - VCC 0.2 P-VCC + 0.3 P-VCC + 0.2 0.2P - VCC 0.4 +1
- - 2.4 P-VCC 0.3 - -0.1 P-VCC 0.3 P-VCC0.4 -0.2 -0.2 -1
10 10 - - 0.4 0.3 P-VCC + 0.2 P-VCC + 0.2 0.5 0.6 +1
A V V V V V V V V A
2, 4 4 5 4 5 4 5 4 5 1, 2
V OH
Output HIGH Voltage
VOL
Output LOW Voltage
IOL = 0.1 mA, VCCMin
VIH
Input HIGH Voltage
V IL IIL
Input LOW Voltage Input Leakage Current Output Leakage Current -0.2 < VIN < P-VCC + 0.2 V -0.2 < VIN < P-VCC + 0.2 V P-VCC = VDR
-1
IOL Notes: 1. 2. 3. 4. 5.
-1
+1
-1
+1
A
1, 2
Input Leakage currents include Hi-Z output leakage for bi-directional buffers with tri-state outputs. All currents are in RMS unless noted otherwise. Applicable only to parts 38F1030W0YxQF & 38F2030W0YxQF. Applicable to parts with P-Mode pin (38F2030W0ZxQ1, 38F2040W0YxQ0, 28F2240WWYxQ0). Applicable to No-P-Mode (38F1030W0YxQF, 38F1030W0YxQ2, 38F1030W0ZxQ0, 38F2030W0YxQ1, 38F2030W0YxQF, 38F2030W0YxQ2, 38F2030W0YxQF, 38F2030W0ZxQ2, 38F2040W0ZxQ0).
November 2007 Order Number: 251407-13
Datasheet 19
32WQ and 64WQ Family with Asynchronous RAM
7.0
7.1
AC Characteristics
Flash AC Characteristics
Refer to the Numonyx Wireless Flash Memory (W18) Datasheet (order number 290701) and Numonyx Wireless Flash Memory (W30) Datasheet (order number 290702)
7.2
Table 9:
# R1 R2 R3 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 Note: 1. 2. 3. 4.
SRAM AC Characteristics
SRAM AC Characteristics
Symbol1 tRC tAA tCO1 tCO2 tOE tBA tLZ tOLZ tHZ tOHZ tOH tBLZ tBHZ Read Cycle Time Address to Output Delay S-CS1# to Output Delay S-CS2 to Output Delay R-OE# to Output Delay R-UB#, R-LB# to Output Delay S-CS1# or S-CS2 to Output in Low-Z R-OE# to Output in Low-Z S-CS1# or S-CS2 to Output in High-Z R-OE# to Output in High-Z Output Hold (from Address, S-CS1#, S-CS2 or R-OE# Change, whichever occurs first) R-UB#, R-LB# to Output in Low-Z R-UB#, R-LB# to Output in High-Z Parameter Min 70 - - - - - 5 0 0 0 0 0 0 Max - 70 70 70 35 70 - - 25 25 - - 25 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Notes 1 1 1 1 1 1 1,3,4 1,4 1,2,3,4 1,2,4 1 1,4 1,4
See Figure 5, "AC Waveform SRAM Read Operations" . Timings of tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. At any given temperature and voltage condition, tHZ (Max) is less than tLZ (Max) both for a given device and from device to device interconnection. Sampled, but not 100% tested.
Datasheet 20
November 2007 Order Number: 251407-13
32WQ and 64WQ Family with Asynchronous RAM
Figure 5:
AC Waveform SRAM Read Operations
Standby
ADDRESSES R3 S-CS1# R6 S-CS2 R7 R-OE# R-WE# R4 R2 DATA R11 R5 R-UB#, R-LB#
R1 Address Stable R8
R9
R10 Valid Data R12
November 2007 Order Number: 251407-13
Datasheet 21
32WQ and 64WQ Family with Asynchronous RAM
Table 10: SRAM AC Characteristics (Write)
# W1 W2 W3 W4 W5 W6 W7 W8 W9 Symbol1 tWC tAS tWP tDW tAW tCW tDH tWR tBW Write Cycle Time Address Setup to R-WE# (S-CS1#) and R-UB#/R-LB# Low R-WE# (S-CS1#) Pulse Width Data to Write Time Overlap Address Setup to R-WE# (S-CS1#) High S-CS1# (R-WE#) Setup to R-WE# (S-CS1#) High Data Hold from R-WE# (S-CS1#) High Write Recovery R-UB#, R-LB# Setup to R-WE# (S-CS1#) High Parameter Min 70 0 55 30 60 60 0 0 60 Max - - - - - - - - - Unit ns ns ns ns ns ns ns ns ns Notes 1 1,4 1,2,3 1 1 1 1 1,5 1
Notes: 1. See Figure 6, "AC Waveform SRAM Write Operations" . 2. A write occurs during the overlap (tWP) of low S-CS1# and low R-WE#. A write begins when S-CS1# goes low and RWE# goes low with asserting R-UB# and R-LB# for single byte operation or simultaneously asserting R-UB#R-LB# and R-LB# for double byte operation. A write ends at the earliest high transition of S-CS1# and R-WE#. 3. tWP is measured from S-CS1# low to the end of a write. 4. tAS is measured from the address valid to the beginning of a write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as S-CS1# or R-WE# goes high.
Figure 6:
AC Waveform SRAM Write Operations
Standby
ADDRESSES
W1 Address Stabl e W6 W8
S-CS1# S-CS2 R-OE# W3 W5 R-WE# W4 DATA W2 R-UB#, R-LB# W9 Data In W7
7.3
PSRAM AC Characteristics
Table 11: PSRAM AC Characteristics (85ns or 88ns Initial Access) -- Read Operations
# R1 R2 R3 Symbol tRC tAA tCO Parameter 5 Min Read Cycle Time Address to Output Delay P-CS# to Output Delay 88 - - 1.8 V Max 4,000 88 88 Min 85 - - 3.0 V Unit Max 4,000 85 85 ns ns ns Notes
Datasheet 22
November 2007 Order Number: 251407-13
32WQ and 64WQ Family with Asynchronous RAM
Table 11: PSRAM AC Characteristics (85ns or 88ns Initial Access) -- Read Operations
# R4 R5 R6 R7 R8 R9 R10 R11 R12 PR1 PR2 Note: 1. 2. 3. 4. 5. Symbol tOE tBA tLZ tOLZ tHZ tOHZ tOH tBLZ tBHZ tPC tPA Parameter5 R-OE# to Output Delay R-UB#, R-LB# to Output Delay P-CS# to Output in Low-Z R-OE# to Output in Low-Z P-CS# to Output in High-Z R-OE# to Output in High-Z Output Hold (from Address, P-CS# or ROE# change, whichever occurs first) R-UB#, R-LB# to Output in Low-Z R-UB#, R-LB# to Output in High-Z Page Cycle Time Page Access Time - - 10 5 - - 5 5 - 30 - 1.8 V Min Max 65 88 - - 25 25 - - 25 - 30 3.0 V Unit Min - - 10 0 0 0 0 0 0 40 - Max 40 85 - - 25 25 - - 25 - 35 ns ns ns ns ns ns ns ns ns ns ns 2 2 4 4 1,2 2 1,2,3 2,3 Notes
At any given temperature and voltage condition, tHZ (Max) is less than tLZ (Max) both for a given device and from device to device interconnection. Sampled but not 100% tested. Timings of tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 4-Word Page read only available for 32-Mbit PSRAM. No page mode feature for 16-Mbit PSRAM. Applicable to parts with 85ns or 88ns initial access time: 38F2030W0ZxQ1, 38F2040W0YxQ0, 38F2040W0ZxQ0, 28F2240WWYxQ0.
November 2007 Order Number: 251407-13
Datasheet 23
32WQ and 64WQ Family with Asynchronous RAM
Table 12: PSRAM AC Characteristics (70ns Initial Access) -- Read Operations
# Symbol1 Parameter 7 70 70 - - - - 5 0 0 0 0 0 0 25 - - 1.8 V Min R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 PR1 PR2 tRC tAA tCO tOE tBA tLZ tOLZ tHZ tOHZ tOH tBLZ tBHZ tPC tPA tCEL Note: 1. 2. 3. 4. 5. 6. 7. Read Cycle Time Address to Output Delay P-CS# to Output Delay R-OE# to Output Delay R-UB#, R-LB# to Output Delay P-CS# to Output in Low-Z R-OE# to Output in Low-Z P-CS# to Output in High-Z R-OE# to Output in High-Z Output Hold (from Address, P-CS# or R-OE# change, whichever occurs first) R-UB#, R-LB# to Output in Low-Z R-UB#, R-LB# to Output in High-Z Page Cycle Time Page Access Time CE# low-time restriction Max 15000 8000 70 70 45 70 - - 25 25 - - 25 - 25 8,000 Min 70 - - - - - 5 0 0 0 0 0 0 25 - ns 3.0 V Unit Max 15000 - 70 70 45 70 - - 25 25 - - 25 - 25 4 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 5 6 3, 4 4 3 Notes
2
Spec's only applicable to parts 38F1030W0YxQF & 38F2030W0YxQF At any given temperature and voltage condition, tHZ (Max) is less than tLZ (Max) both for a given device and from device to device interconnection. Timings of tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 4-Word Page read only available for 16-Mbit PSRAM. No page mode feature for 8-Mbit PSRAM. Parts 38F1030W0YxQF & 38F2030W0YxQF do not support page mode, so this spec will not apply to them CE# must go high and be maintained high for a minimum of 10ns at least once every 8,000ns Applicable to 70ns initial access P-SRAM's ( 38F1030W0YxQ2, 38F1030W0ZxQ0, 38F2030W0YxQ1, 38F2030W0YxQ2, 38F2030W0YxQF, 38F2030W0ZxQ2)
See Figure 7, "AC Waveform of PSRAM Read Operations" on page 25 and Figure 8, "AC Waveform of PSRAM 4-Word Page Read Operation" on page 25
Datasheet 24
November 2007 Order Number: 251407-13
32WQ and 64WQ Family with Asynchronous RAM
Figure 7:
AC Waveform of PSRAM Read Operations
R1 R2
ADDRESSES R3 P-CS# R5 R-UB#, R-LB# R4 R-OE# R7 R11 R6 DATA Valid Data R10 R9 R12 R8
Figure 8:
AC Waveform of PSRAM 4-Word Page Read Operation
R1 R2
A[Max:2]
Vali d Address PR1 Valid Address
A[1:0]
Valid Address R3
Valid Address
Valid Address R8
P-CS# R4 R-OE# R7 R6 DATA
Note:
R9
PR2 Vali d Data
Vali d Data
Vali d Data
Vali d Data
Available only for 32-Mbit PSRAM and line items with 16-Mbit PSRAM (70 ns) 38F2030W0YTQ1, 38F2030W0YBQ1, 38F2030W0ZTQ2, 38F2030W0ZBQ2, 38F1030W0ZTQ0, 38F1030W0ZBQ0. Not applicable to 8-Mbit PSRAM.
v
Table 13: PSRAM AC Characteristics--Write (Sheet 1 of 2)
# Symbol1 Parameter 7 Min W1 W2 W3 W4 tWC tAS tWP tDW Write Cycle Time Address Setup to R-WE# (P-CS#) and R-UB#, R-LB# going low R-WE#(P-CS#) Pulse Width Data to Write Time Overlap 70 0 55 35 1.8 V Max 8000 - - - Min 70 0 55 35 3.0 V Unit Max - - - - ns ns ns ns 4 2,3 Notes
November 2007 Order Number: 251407-13
Datasheet 25
32WQ and 64WQ Family with Asynchronous RAM
Table 13: PSRAM AC Characteristics--Write (Sheet 2 of 2)
# Symbol1 Parameter7 Min W5 W6 W7 W8 W9 tAW tCW tDH tWR tBW tCEL W10 tWPH Address Setup to R-WE# (P-CS#) Going High P-CS# (R-WE#) Setup to R-WE# (P-CS#) Going High Data Hold from R-WE# (P-CS#) High Write Recovery R-UB#, R-LB# Setup to R-WE# (P-CS#) Going High P-CE# low-time restriction Write High Pulse Width 60 60 0 0 60 - 10 1.8 V Max - - - - - 8,000 - Min 60 60 0 0 60 - - 3.0 V Unit Max - - - - - - - ns ns ns ns ns ns ns 7,8 8 5 Notes
Notes: 1. See Figure 9, "AC Waveform PSRAM Write Operation" . 2. A write occurs during the overlap (tWP) of low P-CS# and low R-WE#. A write begins when P-CS# goes low and R-WE# goes low with asserting R-UB# or R-LB# for single byte operation or simultaneously asserting R-UB# and R-LB# for double byte operation. A write ends at the earliest transition when P-CS# goes high and R-WE# goes high. 3. tWP is measured from P-CS# going low to end of a write. 4. tAS is measured from the address valid to the beginning of a write. 5. tWR is measured from the end of a write to the address change. tWR applied in case a write ends as P-CS# or R-WE# going high. 6. W3 is 70 ns for continuous write operations over 50 times. 7. P-CE# must go high and be maintained high for a minimum of 10ns at least once every 8,000ns 8. Spec's only applicable to parts 38F1030W0YxQF & 38F2030W0YxQF 9. Applicable to 38F2020W0ZTQ1, 38F2020W0ZBQ1, 38F2030W0YTQ1, 38F2030W0YBQ1, 38F2030W0ZTQ2, 38F2030W0ZBQ2, 38F1030W0ZTQ0, 38F1030W0ZBQ0.
Figure 9:
AC Waveform PSRAM Write Operation
W1 W2
ADDRESSES W6 P-CS# W9 R-UB#, R-LB# W8 W3 W5 R-WE# W4 DAT A Data In W7
Datasheet 26
November 2007 Order Number: 251407-13
32WQ and 64WQ Family with Asynchronous RAM
7.4
Device AC Test Conditions
Figure 10: Transient Input/Output Reference Waveform
VCCQ , P-VCC
Input
0V
Note:
VCCQ /2, P-VCC/2
Test Points
VCCQ /2, P-VCC/2
Output
AC test inputs are driven to VCCQ, P-VCC for logic "1" and 0.0 V for logic "0". input/output timing begins/ends at VCCQ /2, P-VCC/2. Input rise and fall time (10% to 90%) < 5 ns. Worse case speed occurs at VCC = VCCMin.
Figure 11: Transient Equivalent Testing Load Circuit
Z O = 50 Ohms
I/O Output
50 Ohms
C L = 30 pf
P-VCC /2 = VCCQ /2
Notes: 1. Test configuration component value for worst case specification conditions. 2. CL includes jig capacitance.
November 2007 Order Number: 251407-13
Datasheet 27
32WQ and 64WQ Family with Asynchronous RAM
8.0
Flash Power Consumption
Refer to the Numonyx Wireless Flash Memory (W18) Datasheet (order number 290701) and Numonyx Wireless Flash Memory (W30) Datasheet (order number 290702) for detailed information.
Datasheet 28
November 2007 Order Number: 251407-13
32WQ and 64WQ Family with Asynchronous RAM
9.0
9.1
Device Operation
Bus Operations
Bus operations for the W18/W30 SCSP family involve the following chip enable and output enable signals, respectively: * F1-CE# for Flash Die#1 and F2-CE# for Flash Die#2 * F1-OE# for Flash Die#1 and F2-OE# for Flash Die#2 All other control signals are shared between the two flash die. Table to Table 16 explain the bus operations of products across this SCSP family. Refer to the W18/W30 discrete datasheets (order numbers 290701 and 290702) for single flash die SCSP bus operations.
Table 14: Flash-Only Bus Operations
D[15:0] F1-OE# F2-OE# F-RST# F1-CE# F2-CE# F-WE# F-VPP ADV# Device Mode Notes 2, 3, 4 1, 3, 4, 5 3, 4, 6 4 4 4 Datasheet 29 WAIT
Sync Array Read All Async / Sync Non-Array Read Flash Die#1 Write
H
L
L
H
L
X
Active
H
X
Flash DOUT Flash DOUT Flash DIN Flash High-Z Flash High-Z Flash High-Z
H
L
L
H
X
X VPPL or VPPH X X X
Asserted
H
X
H
L
H
L
X
Asserted
H
X
Output Disable Standby Reset
H H L
L H X
H X X
H X X
X X X
Active High-Z High-Z
X X X
X X X
November 2007 Order Number: 251407-13
32WQ and 64WQ Family with Asynchronous RAM
Table 14: Flash-Only Bus Operations
D[15:0] F1-OE# F2-OE# F-RST# F1-CE# F2-CE# F-WE# F-VPP Device Mode Notes 2, 3, 4 1, 3, 4, 5 3, 4, 6 4 4 4 D[15:0] Flash DOUT SRAM must be in High-Z Flash DOUT Flash DIN Flash High-Z Any SRAM mode allowed Flash High-Z Flash High-Z 1, 2, 3, 5 1, 2, 3, 5, 6 3, 7 5 5 5 Notes ADV# WAIT
Sync Array Read All Async / Sync Non-Array Read Flash Die#2 Write
H
H
X
H
L
X
Active
L
L
Flash DOUT Flash DOUT Flash DIN Flash High-Z Flash High-Z Flash High-Z
H
H
X
H
X
X VPPL or VPPH X X X
Asserted
L
L
H
H
X
L
X
Asserted
L
H
Output Disable Standby Reset
H H L
X X X
X X X
H X X
X X X
Active High-Z High-Z
L H X
H X X
Notes: 1. For asynchronous read operation, both die may be simultaneously selected, but may not simultaneously drive the memory bus. See Section 10.0, "Flash Command Definitions" on page 33 for details regarding flash selection overlap. 2. WAIT is only valid during synchronous flash reads. WAIT is driven if F-CE# is asserted. Refer to the W18 or W30 datasheet (order number 290701 and 29702) for further information regarding WAIT Signal. 3. For either flash die, F[2:1]-OE# and F-WE# should never be asserted simultaneously. If done so on a particular flash die, F[2:1]-OE# will override F-WE#. 4. L means VIL while H means VIH. X can be VIL or VIH for inputs, VPPL, VPPH or VPPLK for F-VPP. 5. Flash CFI query and status register accesses use D[7:0] only, all other reads use D[15:0]. 6. Refer to W18/W30 datasheet for valid DIN during flash writes.
Table 15: Flash + SRAM Bus Operations
F[2:1]-OE# F[2:1]-CE# S-CS1# F-RST# R-UB#, R-LB# R-WE# F-WE# R-OE# S-CS2 F-VPP ADV# WAIT Active Asserted Asserted Active High-Z High-Z
Device
Mode
Sync Array Read Flash Die(#1 or #2) All Async/ Sync Nonarray Read Write Output Disable Standby Reset
H
L
L
H
L
X
H
L
L
H
X
X
H
L
H
L
L
VPPL or VPPH X X X
H H L
L H X
H X X
H X X
X X X
Datasheet 30
November 2007 Order Number: 251407-13
32WQ and 64WQ Family with Asynchronous RAM
Table 15: Flash + SRAM Bus Operations
F[2:1]-OE# F[2:1]-CE# D[15:0] S-CS1# F-RST# R-UB#, R-LB# R-WE# F-WE# R-OE# S-CS2 F-VPP ADV# Notes 1, 4, 8, 2 4, 5, 8, 2 5, 2 5, 8, 2 9, 2 1, 2, 3, 4, 6 1, 2, 3, 4, 6, 7 3, 4, 6, 8 6 6 6 Datasheet 31 Notes WAIT
Device
Mode
Read Flash must be in High-Z Write SRAM Output Disable Standby Data Retention Any flash mode allowed
L L L H X
H H H X L
L X H X
H L H X
L L X X
SRAM DOUT SRAM DIN SRAM High-Z SRAM High-Z SRAM High-Z
Same as SRAM standby
Notes: 1. For asynchronous read operation, all die may be simultaneously selected, but may not simultaneously drive the memory bus. 2. WAIT is only valid during synchronous flash reads. WAIT is driven if F-CE# is asserted. 3. For flash die, F[2:1]-OE# and F-WE# should never be asserted simultaneously. If done so, F[2:1]-OE# will override F-WE#. 4. For SRAM, R-OE# and R-WE# should never be asserted simultaneously. 5. X can be VIL or VIH for inputs, VPPL, VPPH or VPPLK for F-VPP. 6. Flash CFI query and status register accesses use D[7:0] only, all other reads use D[15:0]. 7. Refer to W18 and W30 datasheet for valid DIN during flash writes. 8. The SRAM is enabled and/or disabled with the logical function: S-CS1# OR S-CS2. 9. The SRAM can be placed into data retention mode by lowering S-VCC to the VDR limit when in standby mode.
Table 16: Flash + PSRAM Bus Operations
F[2:1]-OE# F[2:1]-CE# D[15:0] Flash DOUT Flash DOUT Flash DIN Flash High-Z Any PSRAM mode allowed Flash High-Z Flash High-Z P-Mode F-RST# R-UB#, R-LB# R-WE# F-WE# Device R-OE# P-CS# F-VPP ADV# WAIT Active
Mode
Sync Array Read Flash Die(#1 or #2) All Async/ Sync Nonarray Read Write Output Disable Standby Reset
H
L
L
H
L
X
H
L
L
H
X
X
Asserted
PSRAM must be in High-Z
H
L
H
L
X
VPPL or VPPH X X X
Asserted
H H L
L H X
H X X
H X X
X X X
Active High-Z High-Z
November 2007 Order Number: 251407-13
32WQ and 64WQ Family with Asynchronous RAM
Table 16: Flash + PSRAM Bus Operations
F[2:1]-OE# F[2:1]-CE# D[15:0] P-Mode F-RST# R-UB#, R-LB# R-WE# F-WE# Device R-OE# P-CS# F-VPP ADV# Notes 1, 5, 2 5, 2 6, 2 6, 2 6, 9, 2 WAIT
Mode
Read Flash#1 and #2 must be in High-Z Write PSRAM Output Disable Standby Deep PowerDown
L
H
L
H
L
PSRAM DOUT PSRAM DIN PSRAM High-Z PSRAM High-Z PSRAM High-Z
L
H
H
L
L
L
H
H
H
X
Any flash mode allowed
H
H
X
X
X
H
L
X
X
X
Notes: 1. For asynchronous read operation, all die may be simultaneously selected, but may not simultaneously drive the memory bus. For synchronous burst-mode reads, only two die (one flash and the PSRAM) may be simultaneously selected. 2. WAIT is only valid during synchronous flash reads. WAIT is driven if F-CE# is asserted. 3. F1-CE# for Flash Die#1, F2-CE# for Flash Die#2. F1-OE# is for Flash Die#1, F2-OE# for Flash Die#2. 4. For either flash die, F[2:1]-OE# and F-WE# should never be asserted simultaneously. If done so on a particular flash die, F[2:1]-OE# will override F-WE#. 5. For PSRAM, R-OE# and R-WE# should never be asserted simultaneously. 6. X can be VIL or VIH for inputs, VPPL,VPPH or VPPLK for F-VPP. 7. Flash CFI query and status register accesses use D[7:0] only, all other reads use D[15:0]. 8. Refer to W30/W18 datasheet for Valid DIN during flash writes. 9. Deep power-down is not applicable to 38F2020W0ZTQ1, 38F2020W0ZBQ1, 38F2030W0YTQ1, 38F2030W0YBQ1, 38F2030W0ZTQ2, 38F2030W0ZBQ2, 38F1030W0ZTQ0, 38F1030W0ZBQ0.
Datasheet 32
November 2007 Order Number: 251407-13
32WQ and 64WQ Family with Asynchronous RAM
10.0
Flash Command Definitions
Refer to the Numonyx Wireless Flash Memory (W18) Datasheet (order number 290701) and Numonyx Wireless Flash Memory (W30) Datasheet (order number 290702) for detailed information regarding the following:
11.0 12.0 13.0 14.0 15.0
Flash Read Operations Flash Program Operations Flash Erase Operations Flash Security Modes Flash Read Configuration Register
November 2007 Order Number: 251407-13
Datasheet 33
32WQ and 64WQ Family with Asynchronous RAM
16.0
16.1
SRAM Operations
Power-up Sequence and Initialization
The SRAM functionality and reliability are independent of the power-up sequence and power-up slew rate of the core S-VCC. Any power-up sequence and power-up slew rate is possible under use conditions. SRAM reliability is also independent of the powerdown sequence and power-down slew rate of the core S-VCC.
16.2
Data Retention Mode
Table 17: SRAM Data Retention Operation
Symbol tSDR tRDR Note: 1. Parameter Data Retention Set-up Time Data Retention Recovery Time Min 0 tRC Max - - Unit ns ns 1 Notes
tRC is defined in
Table 9, "SRAM AC Characteristics" on page 20.
Figure 12: SRAM Data Retention Operation Waveform--S-CS1# Controlled
tSDR S-VCC S-VCCmin Data Retention Mode tRDR
S-VIHmin
VDR S-CS1# VSS
Datasheet 34
November 2007 Order Number: 251407-13
32WQ and 64WQ Family with Asynchronous RAM
Figure 13: SRAM Data Retention Operation Waveform--S-CS2 Controlled
tSDR S-VCC S-CS2 S-VCCMIN Data Retention Mode tRDR
VDR
VILMAX VSS
November 2007 Order Number: 251407-13
Datasheet 35
32WQ and 64WQ Family with Asynchronous RAM
17.0
17.1
PSRAM Operations
Power-Up Sequence and Initialization
The PSRAM functionality and reliability are independent of the power-up sequence and slew rate of the core P-VCC. Any power-up sequence and slew rate is possible under use conditions. PSRAM reliability are also independent of the power-down sequence and slew rate of the core P-VCC . The following power-up sequence and register setting should be used before starting normal operation. The PSRAM power-up sequence is represented in Figure 14. Following power application, make P-Mode high after fixing P-Mode to a low level for a period of tI1. Make P-CS# high before making P-Mode high. P-CS# and P-Mode are fixed to a high level for period of tI3.
Figure 14: Timing Waveform for Power-Up Sequence
Register Setting Power Up P-VCC tI2 P-CS# tI1 P-MODE tI3
Table 18: Power-Up Sequence Specifications
Parameter tI1 tI2 tI3 Description Power application with P-Mode held low P-CS# high to P-Mode high P-Mode high to P-CS# low Min 50 10 500 Max -- -- -- Unit s ns s Notes 1,2,3
Notes: 1. Toggle P-Mode to low when starting the power-up sequence. 2. tI1 is specified from when the power supply voltage reaches VCCMIN. 3. Does not apply to 38F2020W0ZTQ1, 38F2020W0ZBQ1, 38F2030W0YTQ1, 38F2030W0YBQ1, 38F2030W0ZTQ2, and 38F2030W0ZBQ2, 38F1030W0ZTQ0, 38F1030W0ZBQ0 line items. Valid PSRAM operations for these line items can begin 200 s after P-Vcc has reached P-Vcc min.
17.1.1
16Mbit PSRAM Power-Up Sequence (Non-Page Mode)
For the non-page mode PSRAM (part's RD38F1030W0YQF, PF38F1030W0YQF, RD38F2030W0YQF, PF38F2030W0YQF) the PSRAM functionality and reliability must be independent of the power-up sequence and power-up slew rate of the core Vcc and the I/O Vcc (Vccq.) Any power-up sequence and power-up slew rate is possible under use conditions. PSRAM reliability must also be independent of the power-down sequence and power-down slew rate of the core Vcc and the I/O Vcc (Vccq.) Once power supply voltages have reached the minimum spec value of 1.7V (or higher), CE# must be maintained high for minimum 200us prior to commencing valid PSRAM operation.
Datasheet 36
November 2007 Order Number: 251407-13
32WQ and 64WQ Family with Asynchronous RAM
17.2
Caution:
Standby Mode/ Deep Power-Down Mode
All line items that do not have the P-Mode pine will not have the deep powerdown feature (38F1030W0YxQ2, 38F1030W0ZxQ0, 38F2030W0YxQ1, 38F2030W0YxQ2, 38F2030W0YxQF, 38F2030W0ZxQ2, 38F2040W0ZxQ0). Data is lost during deep power-down mode as shown in the Table below. Wake-up from deep power-down mode involves the same initialization sequence as discussed in Section 17.1, "Power-Up Sequence and Initialization" on page 36.
Mode Standby Deep Power-Down Memory Cell Data Valid Invalid Delay time to go Active 0 ns Start-Up Sequence
Figure 15: Timing Waveform for Entering Deep Power-Down Mode
1 us P-MODE P-CS# Suspend Mode Device Mode Deep Power Down Mode
17.3
Caution:
PSRAM Special Read and Write Constraints
This section will not apply to line items that do not have the P-Mode pine will not have the deep power-down feature (38F1030W0YxQ2, 38F1030W0ZxQ0, 38F2030W0YxQ1, 38F2030W0YxQ2, 38F2030W0YxQF, 38F2030W0ZxQ2, 38F2040W0ZxQ0).
Table 19: PSRAM Special Read Constraints
Description Cannot have sub tRC address toggle for more than 4 s in active mode. Need either a read operation or P-CS# high for tRC in that time frame P-CS# high level pulse width R-UB#/R-LB# high level pulse width R-OE# high level pulse width in active mode (P-CS# low) P-CS# low to R-OE# low Address Skew time (unstable address with P-CS# low) Min N/A 10 10 10 - - Max N/A - - 10,000 10,000 10 Unit - ns ns ns ns ns 2 1 1 Notes
Notes: 1. Toggling of these control signals is not necessary during address controlled read operations. 2. Address skew time (tSKEW ) indicates the following three types of time depending on the condition.
a. When switching P-CS# from high to low, tSKEW is the time from the P-CS# low input point until the next address is determined. b. When switching P-CS# from low to high, tSKEW is the time from the address change start point to the P-CS# high input point. c. When P-CS# is fixed to low, tSKEW is the time from the address start point until the next address is determined.
Since specs are defined for tSKEW only when P-CS# is active, tSKEW is not subject to limitations when P-CS# is switched from high to low following address determination, or when the address is changed after P-CS# is switched from low to high.
November 2007 Order Number: 251407-13
Datasheet 37
32WQ and 64WQ Family with Asynchronous RAM
Table 20: PSRAM Special Write Constraints
Description Need either R-WE# high or P-CS# high for at least tWC time, for every 4us window during write operations. R-OE# high to R-WE# low in active mode (P-CS# low) R-WE# high to R-OE# low in active mode (P-CS# low) Address Skew time (unstable address with P-CS# low) Note: 1. Min N/A 0 10 - Max N/A 10,000 10,000 10 Unit - ns ns ns 1 Notes
Since specs are defined for tSKEW only when P-CS# is active, tSKEW is not subject to limitations when P-CS# is switched from high to low following address determination, or when the address is changed after P-CS# is switched from low to high.
a. When switching P-CS# from high to low, tSKEW is the time from the P-CS# low input point until the next address is determined. b. When switching P-CS# from low to high, t SKEW is the time from the address change start point to the P-CS# high input point. c. When P-CS# is fixed to low, t SKEW is the time from the address start point until the next address is determined.
Address skew time (tSKEW) indicates the following three types of time depending on the condition.
Appendix A Write State Machine
Refer to the Numonyx Wireless Flash Memory (W18) Datasheet (order number 290701) and Numonyx Wireless Flash Memory (W30) Datasheet (order number 290702) for the WSM details.
Appendix B Common Flash Interface
Refer to the Numonyx Wireless Flash Memory (W18) Datasheet (order number 290701) and NumonyxTM Wireless Flash Memory (W30) Datasheet (order number 290702) for the CFI details.
Appendix C Flash Flowcharts
Refer to the NumonyxTM Wireless Flash Memory (W18) Datasheet (order number 290701) and NumonyxTM Wireless Flash Memory (W30) Datasheet (order number 290702) for the flash flowchart details.
Appendix D Additional Information
:
Order Number 290701 290702 251216 Note:
Document NumonyxTM Wireless Flash Memory (W18) Datasheet NumonyxTM Wireless Flash Memory (W30) Datasheet 64-Mbit 1.8 Volt NumonyxTM Wireless Flash Memory SCSP Family Application Note
Contact your local Numonyx or distribution sales office or visit the Numonyx website at http://www.numonyx.com for the most current information on Numonyx Flash memory products, software, and tools.
Datasheet 38
November 2007 Order Number: 251407-13
32WQ and 64WQ Family with Asynchronous RAM
Appendix E Ordering Information (Active Line Items)
Figure 16: Decoder for Flash + RAM SCSP Family Devices
Flash #1 Family
Flash #1
Flash #2
RAM #1
RD3 8 F 2 0 3 0W0ZBQ0
RAM #2
Flash #2 Family
Package
RD = SCSP P F = P b-free S C S P
Device D etails
0-9, A-D = 1 st G eneration, 130 nm nd E -R = 2 G eneration, 90 nm S-Z = 3 rd G eneration, TBD
(note: 90 nm is only 1.8 V I/O )
Product Lin e D esign ator
38F = Flash & R AM Stack D evice
Pinout In dicator
Q = Q U AD + ballout
Flash D ensity
2 = 64-M bit 1 = 32-M bit 0 = N o die
Param eter Locatio n
B = Bottom Param eter T = Top Param eter D = D ual Param eter Y = 1.8 Volt I/O Z = 3 Volt I/O
RA M Density
4 3 2 1 0 = = = = = 32-M bit 16-M bit 8-M bit 4-M bit N o D ie
Voltage
Product Fam ily
W = Intel(R) W ireless Flash M em ory 0 = N o D ie
November 2007 Order Number: 251407-13
Datasheet 39
32WQ and 64WQ Family with Asynchronous RAM
Table 21: Ordering Information on Active Line Items
Flash Component Size in Mbit and Family RAM Size in Mbit and Type Size (mm) Package Product Number Ballout Type PSRAM
32M Flash + 16M PSRAM 16 PSRAM 32 W18 16 PSRAM 32 W30 64M Flash + 16M PSRAM 16 PSRAM 64 W18 16 PSRAM 8 x 10 x 1.2 Quad+ Lead-free PF38F2030W0YTQ1 PF38F2030W0YBQ1 PF38F2030W0YTQ2 PF38F2030W0YBQ2 PF38F2030W0YTQF PF38F2030W0YBQF 8 x 10 x 1.2 Quad+ Lead-free PF38F2030W0ZTQ2 PF38F2030W0ZBQ2 70 ns, No PMODE pin 70 ns, No PMODE pin & Non-Page Mode Support 70 ns, No PMODE pin 16 PSRAM 8 x 10 x 1.2 Quad+ Lead-free 8 x 10 x 1.2 Quad+ Lead-free PF38F1030W0YTQ2 PF38F1030W0YBQ2 PF38F1030W0YTQF PF38F1030W0YBQF PF38F1030W0ZTQ0 PF38F1030W0ZBQ0 70 ns, No PMODE pin & Non-Page Mode Support 70 ns, No PMODE pin
64 W30 64M Flash + 32M PSRAM 64 W18 64 W30
16 PSRAM
32 PSRAM 32 PSRAM
8 x 10 x 1.2 8 x 10 x 1.2
QUAD+ QUAD+
Lead-free Lead-free
PF38F2040W0YTQ0 PF38F2040W0YBQ0 PF38F2040W0ZTQ1 PF38F2040W0ZBQ1
88 ns, with PMODE pin 85 ns, No PMODE pin
Appendix F Ordering Information (Retired Line Items)
Shown here are the decoder for products in the SCSP family with both flash and RAM and the decoder for products in the SCSP family with flash die only (no RAM). The decoders are following by available product combinations.
Datasheet 40
November 2007 Order Number: 251407-13
32WQ and 64WQ Family with Asynchronous RAM
Figure 17: Decoder for Flash + RAM SCSP Family Devices
Flash #1 Family
Flash #1
Flash #2
RAM #1
RD3 8 F 2 0 3 0W0ZBQ0
RAM #2
Flash #2 Family
Package
R D = SC SP PF = Pb-free SC SP
Device Details
0-9, A-D = 1 s t G eneration, 130 nm E-R = 2 nd G eneration, 90 nm S-Z = 3 rd G eneration, TBD
(note: 90 nm is only 1 .8 V I/O )
P rod uct Line Designator
38F = Flash & R AM Stack D evice
P inout Indicator
Q = Q U AD + ballout
Flash Density
2 = 64-M bit 1 = 32-M bit 0 = N o die
P aram eter Location
B = Bottom Param eter T = Top Param eter D = D ual Param eter Y = 1.8 Volt I/O Z = 3 Volt I/O
R AM Density
4 3 2 1 0 = = = = = 32-M bit 16-M bit 8-M bit 4-M bit N o D ie
V oltage
P roduct Fam ily
W = Intel(R) W ireless Flash M em ory 0 = N o D ie
November 2007 Order Number: 251407-13
Datasheet 41
32WQ and 64WQ Family with Asynchronous RAM
Figure 18: Decoder for Flash-Only SCSP Family Devices
Flash 1/2 Family Flash 3/4 Family
Flash #1
Flash #2
Flash #3
RD 4 8 F 2 2 0 0W 0 Z DQ0
Flash #4
Device Details Package
RD = SCSP PF = Pb-free SCSP
0-9, A-D = 1stGeneration, 130 nm E-R = 2nd Generation, 90 nm
(note: 90 nm is only 1.8 V I/O)
S-Z = 3rd Generation, TBD
Product Line Designator
48F = Flash-only Stack Device
Pinout Indicator
Q = QUAD+ Ballout
Flash Density
2 = 64-Mbit 1 = 32-Mbit 0 = No Die
Parameter Location
D = Dual Parameter T = Top Parameter B = Bottom Parameter
Voltage
Y = 1.8 Volt I/O Z = 3 Volt I/O
Product Family
W = Intel(R) Wireless Flash Memory 0 = No Die
Datasheet 42
November 2007 Order Number: 251407-13
32WQ and 64WQ Family with Asynchronous RAM
Table 22: 32WQ and 64WQ W18/W30 SCSP Ordering Information (Flash Only)
Package Flash Component Size (mm) 32 W30 64 W30 64 W18 + 64W18 8 x 10 x 1.2 8 x 10 x 1.2 8 x 10 x 1.2 Type Lead-free Lead-free Leaded Ballout Quad + Quad + Quad + PF48F1000W0ZTQ0 PF48F1000W0ZBQ0 PF48F2000W0ZTQ0 PF48F2000W0ZBQ0 RD48F2200W0YDQ0 Product Number
(1,2,3,4,5)
November 2007 Order Number: 251407-13
Datasheet 43
32WQ and 64WQ Family with Asynchronous RAM
Notes: 1. 2. 3. 4.
W18 = NumonyxTM Wireless Flash Memory (W18); W30 = NumonyxTM Wireless Flash Memory (W30). B = Bottom Parameter, where Flash Die #1, F1-CE# = Bottom Parameter and Flash Die #2, F2-CE# = Top Parameter. T = Top Parameter where Flash Die #1, F1-CE# = Top Parameter and Flash Die #2, F2-CE# = Bottom Parameter. D = Dual Parameter where Flash Die #1, F1-CE# = Bottom Parameter and Flash Die #2, F2-CE# = Top Parameter.
Table 23: 32WQ and 64WQ W18/W30 SCSP Ordering Information (Flash + SRAM)
Flash Component Size in Mbit and Family RAM Size in Mbit and Type 4 SRAM 64 W18 8 SRAM 16 SRAM 8 SRAM 64 W30 16 SRAM 64 W18 + 64 W18 64 W30 + 64 W30 Notes: 1. 2. 3. 4. 16 SRAM 16 SRAM 8 x 10 x 1.2 8 x 10 x 1.4 8 x 10 x 1.4 Leaded Leaded Leaded Quad+ Quad+ Quad+ Package Product Number (1,2,3,4) Size (mm) 8 x 10 x 1.2 8 x 10 x 1.2 8 x 10 x 1.2 8 x 10 x 1.2 Type Leaded Leaded Leaded Leaded Ballout Quad+ Quad+ Quad+ Quad+ RD38F2010W0YTQ0 RD38F2010W0YBQ0 RD38F2020W0YTQ0 RD38F2020W0YBQ0 RD38F2030W0YTQ0 RD38F2030W0YBQ0 RD38F2020W0ZTQ0 RD38F2020W0ZBQ0 RD38F2030W0ZTQ0 RD38F2030W0ZBQ0 RD38F2230WWYDQ0 RD38F2230WWZDQ0
W18 = NumonyxTM Wireless Flash Memory (W18); W30 = NumonyxTM Wireless Flash Memory (W30). B = Bottom Parameter, where Flash Die #1, F1-CE# = Bottom Parameter and Flash Die #2, F2-CE# = Top Parameter. T = Top Parameter where Flash Die #1, F1-CE# = Top Parameter and Flash Die #2, F2-CE# = Bottom Parameter. D = Dual Parameter where Flash Die #1, F1-CE# = Bottom Parameter and Flash Die #2, F2-CE# = Top Parameter.
Table 24: 32WQ & 64WQ W18/W30 SCSP Ordering Information (Flash + PSRAM) (Sheet 1 of 2)
Flash Component Size in Mbit and Family RAM Size in Mbit and Type Size (mm) Package Product Number Ballout Type
(1,2,3,4,5)
PSRAM used
32 W18
16 PSRAM
8 x 10 x 1.2
Quad+
Leaded
RD38F1030W0YTQ2 RD38F1030W0YBQ2 RD38F1030W0ZTQ0 RD38F1030W0ZBQ0 RD38F2030W0YTQ1 RD38F2030W0YBQ1 RD38F2030W0YTQ2 RD38F2030W0YBQ2 RD38F2030W0ZTQ1 RD38F2030W0ZBQ1 RD38F2030W0ZTQ2 RD38F2030W0ZBQ2
70 ns, No PMODE pin & Non-Page Mode Support 70 ns, No PMODE pin 70 ns, No PMODE pin 70 ns, No PMODE pin & Non-Page Mode Support 85 ns, with PMODE pin 70 ns, No PMODE pin
32 W30 64 W18
16 PSRAM 16 PSRAM
8 x 10 x 1.2 8 x 10 x 1.2
Quad+ Quad+
Leaded Leaded
64 W18
16 PSRAM
8 x 10 x 1.2
Quad+
Leaded
64 W30 64 W30
16 PSRAM 16 PSRAM
8 x 10 x 1.2 8 x 10 x 1.2
Quad+ Quad+
Leaded Leaded
Datasheet 44
November 2007 Order Number: 251407-13
32WQ and 64WQ Family with Asynchronous RAM
Table 24: 32WQ & 64WQ W18/W30 SCSP Ordering Information (Flash + PSRAM) (Sheet 2 of 2)
Flash Component Size in Mbit and Family 64 W18 64 W30 64 W30 64 W18 + 64 W18 64 W30 + 64 W30 Notes: 1. 2. 3. 4. 5. RAM Size in Mbit and Type 32 PSRAM 32 PSRAM 32 PSRAM 32 PSRAM 32 PSRAM Size (mm) 8 x 10 x 1.2 8 x 10 x 1.2 8 x 10 x 1.2 8 x 10 x 1.4 8 x 10 x 1.4 Package Product Number Ballout QUAD+ QUAD+ QUAD+ QUAD+ QUAD+ Type Leaded Leaded Leaded Leaded Leaded
(1,2,3,4,5)
PSRAM used
RD38F2040W0YTQ0 RD38F2040W0YBQ0 RD38F2040W0ZTQ0 RD38F2040W0ZBQ0 RD38F2040W0ZTQ1 RD38F2040W0ZBQ1 RD38F2240WWYDQ0(6) RD38F2240WWYDQ1 RD38F2240WWZDQ0 RD38F2240WWZDQ1
88 ns, with PMODE pin 85 ns, No PMODE pin 85 ns, No PMODE pin 88 ns, with PMODE pin 85 ns, No PMODE pin
W18 = NumonyxTM Wireless Flash Memory (W18); W30 = NumonyxTM Wireless Flash Memory (W30). B = Bottom Parameter, where Flash Die #1, F1-CE# = Bottom Parameter and Flash Die #2, F2-CE# = Top Parameter. T = Top Parameter where Flash Die #1, F1-CE# = Top Parameter and Flash Die #2, F2-CE# = Bottom Parameter. D = Dual Parameter where Flash Die #1, F1-CE# = Bottom Parameter and Flash Die #2, F2-CE# = Top Parameter. RD38F2240WWYDQ0 = Engineering Samples; RD38F2240WWYDQ1 = Production
November 2007 Order Number: 251407-13
Datasheet 45
32WQ and 64WQ Family with Asynchronous RAM
Datasheet 46
November 2007 Order Number: 251407-13

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